14th IEEE-NPSS Real Time Conference, 4-11 de Junho de 2005, Estocolmo, Suécia

	A FPGA-Based Multi-Rate Interpolar with Real-Time Rate Change for a JET Test-Bench System
	A. J. N. Batista, D. Alves, N. Cruz, J. Sousa, C. A. F. Varandas, E. Joffrin, R. Felton, J. Farthing e os Contributos JET-EFDA
	Resumo
	Eight independent multi-rate signal interpolators, with real-time change of rate capability, were implemented on a Field Programmable Gate Array. The interpolator main building blocks are a Cascaded Integrator-Comb (CIC) filter and the respective compensation filter. The latter performs a fixed rate change of 4 and was implemented as a 129 taps Finite Impulse Response (FIR) filter. The FIR filter coefficients were attained from the MATLAB® simulation, based on the inverse sinc(x) function. The CIC was designed to have 6 stages (N), a differential delay (M) of 1 and a variable rate change factor (R) ranging from 10 up to 10000. Each interpolator over-samples the multiple data rate digital signals stored at the Joint European Torus (JET) pulse database to a fixed sampling rate of 40 MSPS. These signals are subsequently converted to the analogue domain by 16 bit Digital-to-Analogue Converters to be used as stimulus for testing real-time control tools and systems at JET.